{"id":1840,"date":"2021-11-18T11:20:37","date_gmt":"2021-11-18T19:20:37","guid":{"rendered":"https:\/\/jetic.org\/?page_id=1840"},"modified":"2022-03-28T08:59:17","modified_gmt":"2022-03-28T15:59:17","slug":"csci150-lecture-5-sequential-circuits-design","status":"publish","type":"page","link":"https:\/\/jetic.org\/de\/kurs\/csci-150\/csci150-lecture-5-sequential-circuits-design\/","title":{"rendered":"[CSCI150] Lecture 5: Sequential Circuits Design"},"content":{"rendered":"<p>In Lecture 4, we will start with sequential circuit designs which includes storage units.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">LS26 Part 1 (Lecture + Tutorial): von Neumann Review, What is a Register, Register Design, Register with EN<\/h2>\n\n\n\n<figure class=\"wp-block-embed is-type-video is-provider-youtube wp-block-embed-youtube wp-embed-aspect-16-9 wp-has-aspect-ratio\"><div class=\"wp-block-embed__wrapper\">\n<iframe loading=\"lazy\" title=\"CSCI150: Lecture 5 LS26 Part 1\" width=\"660\" height=\"371\" src=\"https:\/\/www.youtube.com\/embed\/1usNpcJAk2U?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe>\n<\/div><\/figure>\n\n\n\n<p>Highlight:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>von Neumann CPU<ul><li>Control Unit: Interprets instructions, coordinate between Datapath, Memory, and IO <\/li><li>Datapath: contains registers, the storage component within a CPU for temporary info storage. Usually less than 30 registers, each a binary number (say for 64bit CPUs, each a 64bit number).<\/li><li>Calculation require operands to be loaded into then register from memory before taking place in the datapath using arithmetic functional blocks.<\/li><\/ul><\/li><li>Simple Registers<ul><li>Designed using Flip Flops. A 4bit Register will require 4 D Flip Flops.<\/li><li>Loading: register function that loads the register with a new value from D ports<\/li><li>Clearing: register function used to reset a register&#8217;s value to all zeroes<\/li><li>EN: multiple registers often share a single input channel, the additional EN port on register allow one to specify which register should take in new values and which ones should retain their current values.<ul><li>Require D Flip-Flop with EN and Reset. You can use the one provided in the system library or implement your own.<\/li><\/ul><\/li><\/ul><\/li><\/ul>\n\n\n\n<h2 class=\"wp-block-heading\"><meta charset=\"utf-8\">LS26 Part 2 (Lecture): X86 CPU Example, Datapath Architecture overview<\/h2>\n\n\n\n<figure class=\"wp-block-embed is-type-video is-provider-youtube wp-block-embed-youtube wp-embed-aspect-16-9 wp-has-aspect-ratio\"><div class=\"wp-block-embed__wrapper\">\n<iframe loading=\"lazy\" title=\"CSCI150: Lecture 5 LS26 Part 2\" width=\"660\" height=\"371\" src=\"https:\/\/www.youtube.com\/embed\/Lxq-m35Itks?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe>\n<\/div><\/figure>\n\n\n\n<p>Highlights<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>x86 CPU Example<ul><li>Datapath receives commanding signals from Control Unit, stores data inside the register array, and perform calculation, and store the results back into the register array<\/li><\/ul><\/li><li>Simple Datapath Architecture<ul><li>A register array with multiple registers, sharing CLK and sometimes Reset (for simplicity let&#8217;s say it is shared)<\/li><li>A functional block array<\/li><li>Multiplexers to select input to the functional blocks<\/li><li>A feedback bus leading back to the register array, so that new values can be stored within<\/li><\/ul><\/li><\/ul>\n\n\n\n<h2 class=\"wp-block-heading\"><meta charset=\"utf-8\">LS26 Part 3 (Lecture): Register Microoperations<\/h2>\n\n\n\n<figure class=\"wp-block-embed is-type-video is-provider-youtube wp-block-embed-youtube wp-embed-aspect-16-9 wp-has-aspect-ratio\"><div class=\"wp-block-embed__wrapper\">\n<iframe loading=\"lazy\" title=\"CSCI150: Lecture 5 LS26 Part 3\" width=\"660\" height=\"371\" src=\"https:\/\/www.youtube.com\/embed\/REIlolAWnz8?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe>\n<\/div><\/figure>\n\n\n\n<p>Highlights:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>Microoperations<ul><li>Single Register Microoperations: Single (or No) Register as Input, Single Register as Output<ul><li>Assignment, Reg. Transfer, Shifting, Bitwise NOT, Vector, etc. <\/li><\/ul><\/li><li>Multiple Register Microoperations: Multiple Registers provide input<ul><li>Addition, Subtraction. Bitwise AND\/OR\/XOR, Concatenate, etc. <\/li><\/ul><\/li><\/ul><ul><li>VHDL syntax for microoperations<\/li><\/ul><\/li><\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">LS27 (Lecture + Tutorial): Datapath Implementation<\/h2>\n\n\n\n<figure class=\"wp-block-embed is-type-video is-provider-youtube wp-block-embed-youtube wp-embed-aspect-16-9 wp-has-aspect-ratio\"><div class=\"wp-block-embed__wrapper\">\n<iframe loading=\"lazy\" title=\"CSCI150: Lecture 5 LS27\" width=\"660\" height=\"371\" src=\"https:\/\/www.youtube.com\/embed\/WjAsqYGYYcg?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe>\n<\/div><\/figure>\n\n\n\n<p>Highlights:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>Datapath Implementation Tutorial<ul><li>Selecting register to provide input to all functional blocks: using multiplexer<\/li><li>Selecting functional block to perform calculation: using multiplexer<\/li><li>Selecting register to receive calculation results: using Decoder and enabling ports on Registers<\/li><\/ul><\/li><\/ul>","protected":false},"excerpt":{"rendered":"<p>In Lecture 4, we will start with sequential circuit designs which includes storage units. LS26 Part 1 (Lecture + Tutorial): von Neumann Review, What is a Register, Register Design, Register with EN Highlight: von Neumann CPU Control Unit: Interprets instructions, coordinate between Datapath, Memory, and IO Datapath: contains registers, the storage component within a CPU &hellip; <a href=\"https:\/\/jetic.org\/de\/kurs\/csci-150\/csci150-lecture-5-sequential-circuits-design\/\" class=\"more-link\"><span class=\"screen-reader-text\">[CSCI150] Lecture 5: Sequential Circuits Design<\/span> weiterlesen<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":1300,"menu_order":2,"comment_status":"open","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-1840","page","type-page","status-publish","hentry"],"jetpack_sharing_enabled":true,"publishpress_future_action":{"enabled":false,"date":"2026-05-12 07:15:30","action":"change-status","newStatus":"draft","terms":[],"taxonomy":"","extraData":[]},"publishpress_future_workflow_manual_trigger":{"enabledWorkflows":[]},"_links":{"self":[{"href":"https:\/\/jetic.org\/de\/wp-json\/wp\/v2\/pages\/1840","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/jetic.org\/de\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/jetic.org\/de\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/jetic.org\/de\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/jetic.org\/de\/wp-json\/wp\/v2\/comments?post=1840"}],"version-history":[{"count":4,"href":"https:\/\/jetic.org\/de\/wp-json\/wp\/v2\/pages\/1840\/revisions"}],"predecessor-version":[{"id":1970,"href":"https:\/\/jetic.org\/de\/wp-json\/wp\/v2\/pages\/1840\/revisions\/1970"}],"up":[{"embeddable":true,"href":"https:\/\/jetic.org\/de\/wp-json\/wp\/v2\/pages\/1300"}],"wp:attachment":[{"href":"https:\/\/jetic.org\/de\/wp-json\/wp\/v2\/media?parent=1840"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}