{"id":1820,"date":"2021-11-09T15:33:57","date_gmt":"2021-11-09T23:33:57","guid":{"rendered":"https:\/\/jetic.org\/?page_id=1820"},"modified":"2021-11-15T12:12:34","modified_gmt":"2021-11-15T20:12:34","slug":"csci150-lecture-4-sequential-circuits-design","status":"publish","type":"page","link":"https:\/\/jetic.org\/de\/kurs\/csci-150\/csci150-lecture-4-sequential-circuits-design\/","title":{"rendered":"[CSCI150] Lecture 4: Sequential Circuits Design"},"content":{"rendered":"<p>In Lecture 4, we will start with sequential circuit designs which includes storage units.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">LS19 (Lecture): What is Sequential Circuit? SR Latch, notSnotR Latch, D Latch<\/h2>\n\n\n\n<figure class=\"wp-block-embed is-type-video is-provider-youtube wp-block-embed-youtube wp-embed-aspect-16-9 wp-has-aspect-ratio\"><div class=\"wp-block-embed__wrapper\">\n<iframe loading=\"lazy\" title=\"CSCI150: Lecture 4 LS19\" width=\"660\" height=\"371\" src=\"https:\/\/www.youtube.com\/embed\/gw9vaiuc_R8?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe>\n<\/div><\/figure>\n\n\n\n<p>Highlight:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>Sequential Circuit<ul><li>Storage unit: can be used to store partial input, user information, instructions, etc.<\/li><li>Information stored in the storage unit: <strong>states<\/strong><\/li><li>Gives ability to process variable length input and store data in general<\/li><li>Synchronous vs Asynchronous:<ul><li>Clock: at every CLK tick, storage unit is updated with new states while outputting previous state.<\/li><li><strong>Synchronous: all storage unit share one Clock unit (this lecture)<\/strong><\/li><li>Asynchronous: no CLK or more than 1 CLK (not covered in this course)<\/li><\/ul><\/li><\/ul><\/li><li>Latches<ul><li>Basic information storage unit, <strong>maintains internal states indefinitely unless given inputs to change it<\/strong><\/li><li><strong>SR Latch<\/strong>: to change internal state to 1, change the Set port to 1; to change internal state to 0, change the reset port to 1. <strong>Set and Reset cannot both be 1<\/strong>, something unpredictable will happen<\/li><\/ul><ul><li><strong>notSnotR Latch<\/strong>: to change internal state to 1, change the Set port to 0; to change internal state to 0, change the reset port to 0. <strong>Set and Reset cannot both be 0<\/strong>, something unpredictable will happen<\/li><li><strong>D Latch<\/strong>: safer than SR and notSnotR: no unpredictable state. C port controls whether to take in new internal state value from D.<\/li><\/ul><\/li><\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">LS20 (Lecture): Flip-Flops, SR Master-Slave and D Flip-Flop<\/h2>\n\n\n\n<figure class=\"wp-block-embed is-type-video is-provider-youtube wp-block-embed-youtube wp-embed-aspect-16-9 wp-has-aspect-ratio\"><div class=\"wp-block-embed__wrapper\">\n<iframe loading=\"lazy\" title=\"CSCI150: Lecture 4 LS20\" width=\"660\" height=\"371\" src=\"https:\/\/www.youtube.com\/embed\/zFUWaGk6-yw?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe>\n<\/div><\/figure>\n\n\n\n<p>Highlights:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>Transparency: you can see the input from the output, when C is active. This is undesirable for stability<\/li><li>SR Latch with Control pin: additional enabling circuit on the input side<\/li><li>SR Master-Slave Flip-Flop<\/li><li>D Flip-Flop<\/li><\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">LS21 (Lecture + Tutorial): State Table, State Diagram<\/h2>\n\n\n\n<figure class=\"wp-block-embed is-type-video is-provider-youtube wp-block-embed-youtube wp-embed-aspect-16-9 wp-has-aspect-ratio\"><div class=\"wp-block-embed__wrapper\">\n<iframe loading=\"lazy\" title=\"CSCI150: Lecture 4 LS21\" width=\"660\" height=\"371\" src=\"https:\/\/www.youtube.com\/embed\/EQnRx1CITzg?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe>\n<\/div><\/figure>\n\n\n\n<p>Highlights:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>State Table<ul><li>Similar to Truth Table, Input + Present state on the left, Output + Next state on the right<\/li><\/ul><\/li><li>State Diagram<ul><li>Models state transition<\/li><\/ul><ul><li>State bubbles: one for each state<\/li><li>Transition: link from one to another state bubble<\/li><li>Transition condition and output as binary values on next to each transition link<\/li><\/ul><\/li><\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">LS22 (Lecture + Tutorial): D Flip-Flop with Reset, 8 Step Designing Procedure, Formulation<\/h2>\n\n\n\n<figure class=\"wp-block-embed is-type-video is-provider-youtube wp-block-embed-youtube wp-embed-aspect-16-9 wp-has-aspect-ratio\"><div class=\"wp-block-embed__wrapper\">\n<iframe loading=\"lazy\" title=\"CSCI150: Lecture 4 LS22\" width=\"660\" height=\"371\" src=\"https:\/\/www.youtube.com\/embed\/XbzLPvI37cc?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe>\n<\/div><\/figure>\n\n\n\n<p>Highlight:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>Reset stage: asynchronous and synchronous reset<\/li><li>Design an asynchronous reset D flip flop. I find this easier to use to LogicWork simulation<\/li><li>8 step designing procedure<ul><li>Addition to the 5 step for combinational:<ul><li>Step 1: Spec (Same)<\/li><li>Step 2: Formulation<ul><li>State Table and State Diagram instead of truth table<\/li><li>Can use variables for states in this step<\/li><\/ul><\/li><li><strong>Step 3: State Assignment (Next Video)<\/strong><\/li><li><strong>Step 4: Flip-Flop input equation determination (Next Video)<\/strong><\/li><li><strong>Step 5: Output equation determination (Next Video)<\/strong><\/li><li>Step 6: Optimisation (Same)<\/li><li>Step 7: Tech mapping (Same)<\/li><li>Step 8: Verification (Same)<\/li><\/ul><\/li><\/ul><\/li><\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">LS23 (Lecture): Step 3-5 of 8-Step designing procedures; T and JK Flip Flop<\/h2>\n\n\n\n<figure class=\"wp-block-embed is-type-video is-provider-youtube wp-block-embed-youtube wp-embed-aspect-16-9 wp-has-aspect-ratio\"><div class=\"wp-block-embed__wrapper\">\n<iframe loading=\"lazy\" title=\"CSCI150: Lecture 4 LS23\" width=\"660\" height=\"371\" src=\"https:\/\/www.youtube.com\/embed\/QNyjq7wttdc?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe>\n<\/div><\/figure>\n\n\n\n<p>Highlights:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>Step 3: State Assignment<ul><li><strong>No unique solution, we only cover two methods<\/strong><\/li><li><strong>Sequential Assignment<\/strong><ul><li>given N states, assign binary values of 0 to N-1 sequentially<\/li><li>Require log(n) bits<\/li><li>e.g. 6 states, require 3 bits: 000, 001, 010, 011, 100, 101 (or in any other order, all correct but not equivalent)<\/li><li><strong>Different order leads to different circuit<\/strong><\/li><\/ul><\/li><\/ul><ul><li><strong>One-hot Assignment<\/strong><ul><li>given N states, require N bits<\/li><li>Each state is N bit, with only a single positive bit, the reset are zeroes.<\/li><li>e.g. 6 states, require 6 bits: 000001, 000010, 000100, 001000, 010000, 100000 (or in any other order, all equivalent)<\/li><li><strong>Different order leads to identical circuit<\/strong><\/li><\/ul><\/li><\/ul><\/li><li>Step 4, 5: Flip-Flop input equation determination and Output equation determination<ul><li>From state table: Sum-of-Minterm, then optimise<\/li><\/ul><ul><li>Use unused states as Don&#8217;t Care Conditions<\/li><\/ul><\/li><li>T and JK Flip-Flop<ul><li>Can be implemented using D Flip-Flops<\/li><li>T Flip-Flop<ul><li>Input ports: T, and C<\/li><\/ul><ul><li>Flip internal signal with T is 1<\/li><\/ul><\/li><li>JK Flip-Flop<ul><li>Input ports: J, K, and C<\/li><li>J for Set, K for Reset, just like SR Flip-Flop<\/li><li>Flip internal value with J and K are both 1<\/li><\/ul><\/li><\/ul><\/li><\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">LS24 (Lecture): Moore Model\/State Machine Diagram<\/h2>\n\n\n\n<figure class=\"wp-block-embed is-type-video is-provider-youtube wp-block-embed-youtube wp-embed-aspect-16-9 wp-has-aspect-ratio\"><div class=\"wp-block-embed__wrapper\">\n<iframe loading=\"lazy\" title=\"CSCI150: Lecture 4 LS24\" width=\"660\" height=\"371\" src=\"https:\/\/www.youtube.com\/embed\/Nj6xJP7NIKo?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe>\n<\/div><\/figure>\n\n\n\n<p>Highlights:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>State Diagrams (Mealy Model) can be inefficient when you have more input\/output bits<\/li><li>State Machine Diagrams (Moore Model): Instead of binary values for transitions and output, use Boolean Expressions<ul><li>3 Steps to go from State Diagrams to Moore model<ul><li>Preserve all state bubbles and transition links<\/li><li>Translate binary transition conditions into boolean expressions<\/li><li>Note the default output values, then add output conditions on Transition Conditions or States<\/li><\/ul><\/li><\/ul><\/li><\/ul>","protected":false},"excerpt":{"rendered":"<p>In Lecture 4, we will start with sequential circuit designs which includes storage units. LS19 (Lecture): What is Sequential Circuit? SR Latch, notSnotR Latch, D Latch Highlight: Sequential Circuit Storage unit: can be used to store partial input, user information, instructions, etc. Information stored in the storage unit: states Gives ability to process variable length &hellip; <a href=\"https:\/\/jetic.org\/de\/kurs\/csci-150\/csci150-lecture-4-sequential-circuits-design\/\" class=\"more-link\"><span class=\"screen-reader-text\">[CSCI150] Lecture 4: Sequential Circuits Design<\/span> weiterlesen<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":1300,"menu_order":2,"comment_status":"open","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-1820","page","type-page","status-publish","hentry"],"jetpack_sharing_enabled":true,"publishpress_future_action":{"enabled":false,"date":"2026-06-01 17:36:33","action":"change-status","newStatus":"draft","terms":[],"taxonomy":"","extraData":[]},"publishpress_future_workflow_manual_trigger":{"enabledWorkflows":[]},"_links":{"self":[{"href":"https:\/\/jetic.org\/de\/wp-json\/wp\/v2\/pages\/1820","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/jetic.org\/de\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/jetic.org\/de\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/jetic.org\/de\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/jetic.org\/de\/wp-json\/wp\/v2\/comments?post=1820"}],"version-history":[{"count":11,"href":"https:\/\/jetic.org\/de\/wp-json\/wp\/v2\/pages\/1820\/revisions"}],"predecessor-version":[{"id":1838,"href":"https:\/\/jetic.org\/de\/wp-json\/wp\/v2\/pages\/1820\/revisions\/1838"}],"up":[{"embeddable":true,"href":"https:\/\/jetic.org\/de\/wp-json\/wp\/v2\/pages\/1300"}],"wp:attachment":[{"href":"https:\/\/jetic.org\/de\/wp-json\/wp\/v2\/media?parent=1820"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}