{"id":1764,"date":"2021-10-11T18:46:22","date_gmt":"2021-10-12T01:46:22","guid":{"rendered":"https:\/\/jetic.org\/?page_id=1764"},"modified":"2021-11-09T11:24:30","modified_gmt":"2021-11-09T19:24:30","slug":"csci150-lecture-3-combinational-circuits-design","status":"publish","type":"page","link":"https:\/\/jetic.org\/de\/kurs\/csci-150\/csci150-lecture-3-combinational-circuits-design\/","title":{"rendered":"[CSCI150] Lecture 3: Combinational Circuits Design"},"content":{"rendered":"<p>Lecture 2 deals mainly with Boolean Algebra, the theoretical arsenal for circuit design. In Lecture 3, we will learn more practical design procedures, as well as functional blocks.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">LS9 Part 1 (Lecture): Systematic Designing Procedures, Curtain Controller Example<\/h2>\n\n\n\n<figure class=\"wp-block-embed is-type-video is-provider-youtube wp-block-embed-youtube wp-embed-aspect-16-9 wp-has-aspect-ratio\"><div class=\"wp-block-embed__wrapper\">\n<iframe loading=\"lazy\" title=\"CSCI150: Lecture 3 LS9 (Lecture)\" width=\"660\" height=\"371\" src=\"https:\/\/www.youtube.com\/embed\/kMGb6eklmNI?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe>\n<\/div><\/figure>\n\n\n\n<p>Highlight:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>5 Step Systematic Designing Procedures<ul><li><strong>Specification<\/strong>: (Provided, includes I\/O ports and description in human language of the system)<\/li><li><strong>Formulation<\/strong>: transform spec into Truth Table or simple Boolean Expressions<\/li><li><strong>Optimisation<\/strong>: transform what you have in formulation into simplest forms (usually in boolean expressions, or later, functional blocks), so that it requires less gates and components in general to implement<\/li><li><strong>Technology Mapping<\/strong>: <ul><li>Technology: physical components you can use to implement, so far that includes gates and I\/O devices (in LogicWorks, Binary Switch and Prob)<\/li><li>Mapping: use available technology to implement your circuit<\/li><\/ul><\/li><li><strong>Verification<\/strong>: test to see if your circuit meets the specification, or else go to debugging<\/li><\/ul><\/li><\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">LS9 Part 2: Curtain Motor Controller Example in LogicWorks<\/h2>\n\n\n\n<figure class=\"wp-block-embed is-type-video is-provider-youtube wp-block-embed-youtube wp-embed-aspect-16-9 wp-has-aspect-ratio\"><div class=\"wp-block-embed__wrapper\">\n<iframe loading=\"lazy\" title=\"CSCI150: Lecture 3 LS9 (Tutorial)\" width=\"660\" height=\"371\" src=\"https:\/\/www.youtube.com\/embed\/IrDGujGWTkw?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe>\n<\/div><\/figure>\n\n\n\n<p>Highlights:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>Steps<ol><li>Do the I\/O ports using binary switches and probs<\/li><li>Do the names of I\/O ports according to your optimised boolean expressions<\/li><li>Start from the easiest connections, utilise the available technology and proceed gradually to the output<\/li><li>Test connections by clicking the wires always<\/li><li>Test the overall circuit (perform Verification essentially)<\/li><\/ol><\/li><\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">LS10 Part 1: BCD-to-7-Segment-Display Example (Lecture + Tutorial)<\/h2>\n\n\n\n<figure class=\"wp-block-embed is-type-video is-provider-youtube wp-block-embed-youtube wp-embed-aspect-16-9 wp-has-aspect-ratio\"><div class=\"wp-block-embed__wrapper\">\n<iframe loading=\"lazy\" title=\"CSCI150: Lecture 3 LS10 Part 1\" width=\"660\" height=\"371\" src=\"https:\/\/www.youtube.com\/embed\/USC5J4ovF0E?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe>\n<\/div><\/figure>\n\n\n\n<p>Highlight<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>LogicWorks components<ul><li>Hex Keyboard (use the one without STB port)<\/li><li>7 Segment Display<\/li><li>AND\/OR gates with more than 2 inputs (and some of them inverted)<\/li><\/ul><\/li><\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">LS10 Part 2: Custom Components out of Existing Design (Tutorial)<\/h2>\n\n\n\n<figure class=\"wp-block-embed is-type-video is-provider-youtube wp-block-embed-youtube wp-embed-aspect-16-9 wp-has-aspect-ratio\"><div class=\"wp-block-embed__wrapper\">\n<iframe loading=\"lazy\" title=\"CSCI150: Lecture 3 LS10 Part 2\" width=\"660\" height=\"371\" src=\"https:\/\/www.youtube.com\/embed\/Tp31rDUnKkY?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe>\n<\/div><\/figure>\n\n\n\n<p>Highlight:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>How to create a custom part<ol><li>New Device Symbol<\/li><li>Options -&gt; Sub-circuit and Part Type<\/li><li>Create sub-circuit symbol and select an open circuit to attach to it<\/li><li>Draw the box, and pins<\/li><li>Give it a name<\/li><li>Create your own library<\/li><li>Save the component in your library<\/li><li>Reward yourself some ice cream\ud83c\udf66<\/li><\/ol><\/li><\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">LS10 Part 3: Hierarchical Design, 4-bit Equity Comparator (Lecture + Tutorial)<\/h2>\n\n\n\n<figure class=\"wp-block-embed is-type-video is-provider-youtube wp-block-embed-youtube wp-embed-aspect-16-9 wp-has-aspect-ratio\"><div class=\"wp-block-embed__wrapper\">\n<iframe loading=\"lazy\" title=\"CSCI150: Lecture 3 LS10 Part 3\" width=\"660\" height=\"371\" src=\"https:\/\/www.youtube.com\/embed\/AocId4ufeAc?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe>\n<\/div><\/figure>\n\n\n\n<p>Highlight<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>Hierarchical Design<ul><li>Divide and Conquer: break up a difficult problem into easier smaller problems, and solve<\/li><li>Functional Blocks: a complete circuit in its own right, that you can easily reuse just like gates in other designs.<ul><li>In hierarchical designs, you can implement blocks functional blocks that are easier to do to save time<\/li><li>Each block should also be defined using 5-step designing procedures<\/li><li>Functional blocks are considered technology in<strong> Step4 of Systematic Designing Procedures<\/strong><\/li><\/ul><\/li><\/ul><\/li><\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">LS10 Part 4: Few words on Tech Mapping &amp; Auto Verification (Lecture)<\/h2>\n\n\n\n<figure class=\"wp-block-embed is-type-video is-provider-youtube wp-block-embed-youtube wp-embed-aspect-16-9 wp-has-aspect-ratio\"><div class=\"wp-block-embed__wrapper\">\n<iframe loading=\"lazy\" title=\"CSCI150: Lecture 3 LS10 Part 4\" width=\"660\" height=\"371\" src=\"https:\/\/www.youtube.com\/embed\/eAQZvtkGRjY?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe>\n<\/div><\/figure>\n\n\n\n<p>Highlight:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>Technology Mapping<ul><li>Replacing everything with NAND and Inverters<\/li><li>FPGA: Field Programmable Gating Array<ul><li>Programmable circuit boards<\/li><li>You write the circuit in Hardware Description Language, then upload to the board. The board will then work like your designed circuit<\/li><li>Not a von Neumann Computer<\/li><\/ul><\/li><\/ul><\/li><li>Verification<ul><li>Manual &amp; Auto: the latter uses computer assisted stuff<\/li><\/ul><\/li><\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">LS11 Part 1: Elementary Functional Blocks (Lecture)<\/h2>\n\n\n\n<figure class=\"wp-block-embed is-type-video is-provider-youtube wp-block-embed-youtube wp-embed-aspect-16-9 wp-has-aspect-ratio\"><div class=\"wp-block-embed__wrapper\">\n<iframe loading=\"lazy\" title=\"CSCI150: Lecture 3 LS11 Part 1\" width=\"660\" height=\"371\" src=\"https:\/\/www.youtube.com\/embed\/rRQ3xowzTuY?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe>\n<\/div><\/figure>\n\n\n\n<p>Highlights:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>Elementary Functional Blocks<ol><li>Value Fixing: provide constant values of 0 and 1 to a wire<\/li><li>Value Transferring: provide the value of one wire to another<\/li><li>Inverting: NOT gate operation<\/li><li>Vector denotation: bus formulation (also called breakouts in LogicWorks)<\/li><li>Enabler: if EN signal is 1, works just like transferring for input X; if EN is 0, always output 0.<\/li><\/ol><\/li><\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">LS11 Part 2: Elementary Functional Blocks (Tutorial)<\/h2>\n\n\n\n<figure class=\"wp-block-embed is-type-video is-provider-youtube wp-block-embed-youtube wp-embed-aspect-16-9 wp-has-aspect-ratio\"><div class=\"wp-block-embed__wrapper\">\n<iframe loading=\"lazy\" title=\"CSCI150: Lecture 3 LS11 Part 2\" width=\"660\" height=\"371\" src=\"https:\/\/www.youtube.com\/embed\/OexTP4nAypc?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe>\n<\/div><\/figure>\n\n\n\n<p>Highlights:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>Implementing Elementary Functional Blocks<ol><li>Value Fixing: use +5V for constant 1, digital ground for 0<\/li><li>Value Transferring: connect the wire, that&#8217;s it<\/li><li>Inverting: use the NOT gate<\/li><li>Vector denotation: use breakouts(busses) in LogicWorks, the thicker wire is used for connecting these busses<\/li><li>Enabler: an AND gate with input EN and X, outputs F<\/li><\/ol><\/li><\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">LS11 Part 3: 1-to-2 and 2-to-4 Decoders (Lecture + Tutorial)<\/h2>\n\n\n\n<figure class=\"wp-block-embed is-type-video is-provider-youtube wp-block-embed-youtube wp-embed-aspect-16-9 wp-has-aspect-ratio\"><div class=\"wp-block-embed__wrapper\">\n<iframe loading=\"lazy\" title=\"CSCI150: Lecture 3 LS11 Part 3\" width=\"660\" height=\"371\" src=\"https:\/\/www.youtube.com\/embed\/nnCL9mmnB8Q?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe>\n<\/div><\/figure>\n\n\n\n<p>Highlights:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>1-to-2 Decoder, and its implementation in logicworks<\/li><li>2-to-4 Decoder, and its implementation in logicworks<ol><li>Using standard gates etc.<\/li><li>Using hierarchical design, with 1-to-2 decoder<\/li><li>Using 1-to-2 decoder and busses<\/li><\/ol><\/li><li>It is very important that you try to implement these on your own as well. Remember to create them in your library.<\/li><\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">LS11 Part 4: 3-to-8 and 4-to-16 Decoders (Lecture + Tutorial)<\/h2>\n\n\n\n<figure class=\"wp-block-embed is-type-video is-provider-youtube wp-block-embed-youtube wp-embed-aspect-16-9 wp-has-aspect-ratio\"><div class=\"wp-block-embed__wrapper\">\n<iframe loading=\"lazy\" title=\"CSCI150: Lecture 3 LS11 Part 4\" width=\"660\" height=\"371\" src=\"https:\/\/www.youtube.com\/embed\/Va27JHCpfvA?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe>\n<\/div><\/figure>\n\n\n\n<p>Highlights:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>3-to-8 Decoder<ul><li>Using 2-to-4 Decoder, and busses<\/li><\/ul><\/li><li>4-to-16 Decoder:<ul><li>Incremental design: use 3-to-8 decoder, and busses<\/li><li>Recursive design: use (4\/2 = 2)-to-4 decoder(s), and busses<\/li><\/ul><\/li><\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">LS11 Part 5: 1-bit Binary Adder using Decoder (Lecture + Tutorial)<\/h2>\n\n\n\n<figure class=\"wp-block-embed is-type-video is-provider-youtube wp-block-embed-youtube wp-embed-aspect-16-9 wp-has-aspect-ratio\"><div class=\"wp-block-embed__wrapper\">\n<iframe loading=\"lazy\" title=\"CSCI150: Lecture 3 LS11 Part 5\" width=\"660\" height=\"371\" src=\"https:\/\/www.youtube.com\/embed\/3w3KKhcCeCM?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe>\n<\/div><\/figure>\n\n\n\n<p>Highlights:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>1-bit Binary Adder<ul><li>Input (all 1 bit): X (addend), Y (augend), Z (previous carry)<\/li><li>Output (all 1bit): S (sum), C (next carry)<\/li><li>Use Sum-of-Minterm and decoder to implement with ease, and save as a component in your LogicWorks Library<\/li><\/ul><\/li><\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">LS12: Enabler &amp; Priority Enabler; Multiplexers<\/h2>\n\n\n\n<figure class=\"wp-block-embed is-type-video is-provider-youtube wp-block-embed-youtube wp-embed-aspect-16-9 wp-has-aspect-ratio\"><div class=\"wp-block-embed__wrapper\">\n<iframe loading=\"lazy\" title=\"CSCI150: Lecture 3 LS12\" width=\"660\" height=\"371\" src=\"https:\/\/www.youtube.com\/embed\/BpKKK_4VuDE?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe>\n<\/div><\/figure>\n\n\n\n<p>Highlights:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>Enabler: reverse function of decoders<ul><li>Problem: Invalid input leads to problems, including all 0 inputs and multiple 1s in the input<\/li><\/ul><\/li><li>Priority Enabler:<ul><li>Additional validity bit, equals 1 if input contains 1<\/li><li>Priority: <p class=\"ql-center-displayed-equation\" style=\"line-height: 14px;\"><span class=\"ql-right-eqno\"> &nbsp; <\/span><span class=\"ql-left-eqno\"> &nbsp; <\/span><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/jetic.org\/wp-content\/ql-cache\/quicklatex.com-ef2fa3bf368f07f4352c60c47f04f4ea_l3.png\" height=\"14\" width=\"20\" class=\"ql-img-displayed-equation quicklatex-auto-format\" alt=\"&#92;&#91;&#68;&#95;&#105;&#92;&#93;\" title=\"Rendered by QuickLaTeX.com\"\/><\/p> has higher priority than <p class=\"ql-center-displayed-equation\" style=\"line-height: 15px;\"><span class=\"ql-right-eqno\"> &nbsp; <\/span><span class=\"ql-left-eqno\"> &nbsp; <\/span><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/jetic.org\/wp-content\/ql-cache\/quicklatex.com-18553cd75b783c31752ca8f4fe954dac_l3.png\" height=\"15\" width=\"31\" class=\"ql-img-displayed-equation quicklatex-auto-format\" alt=\"&#92;&#91;&#68;&#95;&#123;&#60;&#105;&#125;&#92;&#93;\" title=\"Rendered by QuickLaTeX.com\"\/><\/p><\/li><\/ul><\/li><li>Multiplexer<ul><li>Switching between multiple channels<\/li><li>Each channel can have N-bits<\/li><li>Switch signal (S) controls which input channel to output<\/li><li>M-Channel N-bit Multiplexer can be designed using N x M-Channel 1-bit Multiplexers<\/li><\/ul><\/li><\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">LS13: Full Adders (Lecture + Tutorial)<\/h2>\n\n\n\n<figure class=\"wp-block-embed is-type-video is-provider-youtube wp-block-embed-youtube wp-embed-aspect-16-9 wp-has-aspect-ratio\"><div class=\"wp-block-embed__wrapper\">\n<iframe loading=\"lazy\" title=\"CSCI150: Lecture 3 LS13\" width=\"660\" height=\"371\" src=\"https:\/\/www.youtube.com\/embed\/Sle-6R_j0uQ?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe>\n<\/div><\/figure>\n\n\n\n<p>Highlights:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>1-bit Half Adder<\/li><li>1-bit Full Adder using Half Adders<ul><li>Hierarchical design<\/li><li>Simpler than using decoder<\/li><\/ul><\/li><li>n-bit Full Adder<ul><li>Ripple Carry Adder using 1-bit Full Adders<\/li><\/ul><\/li><\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">LS14: Subtractors: Unsigned Binary Subtractor I  (Lecture + Tutorial)<\/h2>\n\n\n\n<figure class=\"wp-block-embed is-type-video is-provider-youtube wp-block-embed-youtube wp-embed-aspect-16-9 wp-has-aspect-ratio\"><div class=\"wp-block-embed__wrapper\">\n<iframe loading=\"lazy\" title=\"CSCI150: Lecture 3 LS14\" width=\"660\" height=\"371\" src=\"https:\/\/www.youtube.com\/embed\/YDdLNZNBfog?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe>\n<\/div><\/figure>\n\n\n\n<p>Highlights:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>Standard Unsigned Subtractor: X &#8211; Y, X &gt;= Y<\/li><li>1-bit Subtractor using decoder<\/li><li>n-bit Subtractor using 1-bit Subtractors<\/li><\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">LS15 Part 1: Unsigned 2s Complement, Adder-Subtractor (Lecture + Tutorial)<\/h2>\n\n\n\n<figure class=\"wp-block-embed is-type-video is-provider-youtube wp-block-embed-youtube wp-embed-aspect-16-9 wp-has-aspect-ratio\"><div class=\"wp-block-embed__wrapper\">\n<iframe loading=\"lazy\" title=\"CSCI150: Lecture 3 LS15 Part 1\" width=\"660\" height=\"371\" src=\"https:\/\/www.youtube.com\/embed\/kmLQbeHdpoI?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe>\n<\/div><\/figure>\n\n\n\n<p>Highlights:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>Unsigned 2s Complementer<ul><li>Given n-bit binary integer (unsigned) D<\/li><\/ul><ul><li>the unsigned 2s complement of D: <p class=\"ql-center-displayed-equation\" style=\"line-height: 18px;\"><span class=\"ql-right-eqno\"> &nbsp; <\/span><span class=\"ql-left-eqno\"> &nbsp; <\/span><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/jetic.org\/wp-content\/ql-cache\/quicklatex.com-1683e8f83a43c5834d73ba5b5f1971a9_l3.png\" height=\"18\" width=\"167\" class=\"ql-img-displayed-equation quicklatex-auto-format\" alt=\"&#92;&#91;&#68;&#39;&#32;&#61;&#32;&#50;&#94;&#110;&#32;&#45;&#32;&#68;&#32;&#61;&#32;&#92;&#111;&#118;&#101;&#114;&#108;&#105;&#110;&#101;&#123;&#68;&#125;&#32;&#43;&#32;&#49;&#92;&#93;\" title=\"Rendered by QuickLaTeX.com\"\/><\/p><\/li><li>the unsigned 2s complement of D is equal to, bitwise invert of D plus 1<\/li><\/ul><\/li><li>Correcting X-Y when Y &gt; X<ul><li>If the borrow bit output of your subtractor is 1, excessive values are not correctly subtracted from X, you need correction<\/li><li>Correct output: negative unsigned 2s complement of output D<\/li><li>Design a selective 2s complementer using Adder and XOR, plug into the subtractor<\/li><\/ul><\/li><li>Adder-Subtractor Unit<ul><li>Input vectors X, Y, Mode selector Subtract\/notAdd<\/li><li>Output vector D<\/li><li>Mode Selector is 0, output X+Y<\/li><li>Mode Selector is 1, output X-Y<\/li><li>Use 2channel 4bit Multiplexer (4bit 2-to-1 Multiplexer) to implement<\/li><\/ul><\/li><\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">LS15 Part 2: Subtraction using Adder<\/h2>\n\n\n\n<figure class=\"wp-block-embed is-type-video is-provider-youtube wp-block-embed-youtube wp-embed-aspect-16-9 wp-has-aspect-ratio\"><div class=\"wp-block-embed__wrapper\">\n<iframe loading=\"lazy\" title=\"CSCI150: Lecture 3 LS15 Part 2\" width=\"660\" height=\"371\" src=\"https:\/\/www.youtube.com\/embed\/XiXDNfxbjIk?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe>\n<\/div><\/figure>\n\n\n\n<p>Highlights:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>Subtraction using unsigned 2s complement<ul><li>2s comp of Y = 2^n &#8211; Y<\/li><li>X &#8211; Y = X + (2^n &#8211; Y) &#8211; 2^n = X + Y&#8217; &#8211; 2^n<\/li><li>2^n can be ignored because it is beyond n-bit<\/li><\/ul><\/li><li>Revised simpler Adder-Subtractor<ul><li>XOR and Sub\/notAdd input toggles between Y and Y&#8217;<\/li><li>Output X + Y when Sub\/notAdd = 0<\/li><li>Output X + notY + 1 = X &#8211; Y when Sub\/notAdd = 1<\/li><\/ul><\/li><\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">LS16: Overflow, Signed Arithmetics, Other Functions<\/h2>\n\n\n\n<figure class=\"wp-block-embed is-type-video is-provider-youtube wp-block-embed-youtube wp-embed-aspect-16-9 wp-has-aspect-ratio\"><div class=\"wp-block-embed__wrapper\">\n<iframe loading=\"lazy\" title=\"CSCI150: Lecture 3 LS16\" width=\"660\" height=\"371\" src=\"https:\/\/www.youtube.com\/embed\/v5EjU7_JAck?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe>\n<\/div><\/figure>\n\n\n\n<p>Highlights:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>Overflow, definition and how to use carry\/borrow bit to detect<\/li><li>Signed 2s Complement<ul><li>For signed integers only<\/li><li>For positive, no change<\/li><li>For negative, do NOT change the sign bit, all magnitude bits inverted and plus 1<\/li><\/ul><\/li><li>Signed Arithmetics (addition and subtraction Only)<ul><li>Step 1: Convert both signed numbers to signed 2s complement<\/li><li>Step 2: Perform addition and subtraction using unsigned components<\/li><li>Step 3: Convert result back using signed 2s complement<\/li><\/ul><\/li><li>Others<ul><li>Increment\/Decrement<\/li><li>Multiplier\/Divisor by constant<\/li><li>Others: extensions etc.<\/li><\/ul><\/li><\/ul>","protected":false},"excerpt":{"rendered":"<p>Lecture 2 deals mainly with Boolean Algebra, the theoretical arsenal for circuit design. In Lecture 3, we will learn more practical design procedures, as well as functional blocks. LS9 Part 1 (Lecture): Systematic Designing Procedures, Curtain Controller Example Highlight: 5 Step Systematic Designing Procedures Specification: (Provided, includes I\/O ports and description in human language of &hellip; <a href=\"https:\/\/jetic.org\/de\/kurs\/csci-150\/csci150-lecture-3-combinational-circuits-design\/\" class=\"more-link\"><span class=\"screen-reader-text\">[CSCI150] Lecture 3: Combinational Circuits Design<\/span> weiterlesen<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":1300,"menu_order":2,"comment_status":"open","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-1764","page","type-page","status-publish","hentry"],"jetpack_sharing_enabled":true,"publishpress_future_action":{"enabled":false,"date":"2026-05-12 07:21:46","action":"change-status","newStatus":"draft","terms":[],"taxonomy":"","extraData":[]},"publishpress_future_workflow_manual_trigger":{"enabledWorkflows":[]},"_links":{"self":[{"href":"https:\/\/jetic.org\/de\/wp-json\/wp\/v2\/pages\/1764","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/jetic.org\/de\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/jetic.org\/de\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/jetic.org\/de\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/jetic.org\/de\/wp-json\/wp\/v2\/comments?post=1764"}],"version-history":[{"count":22,"href":"https:\/\/jetic.org\/de\/wp-json\/wp\/v2\/pages\/1764\/revisions"}],"predecessor-version":[{"id":1819,"href":"https:\/\/jetic.org\/de\/wp-json\/wp\/v2\/pages\/1764\/revisions\/1819"}],"up":[{"embeddable":true,"href":"https:\/\/jetic.org\/de\/wp-json\/wp\/v2\/pages\/1300"}],"wp:attachment":[{"href":"https:\/\/jetic.org\/de\/wp-json\/wp\/v2\/media?parent=1764"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}