[CSCI150] Lecture 4: Sequential Circuits Design

In Lecture 4, we will start with sequential circuit designs which includes storage units.

LS19 (Lecture): What is Sequential Circuit? SR Latch, notSnotR Latch, D Latch

Highlight:

Sequential Circuit
- Storage unit: can be used to store partial input, user information, instructions, etc.
- Information stored in the storage unit: states
- Gives ability to process variable length input and store data in general
- Synchronous vs Asynchronous:
  - Clock: at every CLK tick, storage unit is updated with new states while outputting previous state.
  - Synchronous: all storage unit share one Clock unit (this lecture)
  - Asynchronous: no CLK or more than 1 CLK (not covered in this course)
Latches
- Basic information storage unit, maintains internal states indefinitely unless given inputs to change it
- SR Latch: to change internal state to 1, change the Set port to 1; to change internal state to 0, change the reset port to 1. Set and Reset cannot both be 1, something unpredictable will happen
- notSnotR Latch: to change internal state to 1, change the Set port to 0; to change internal state to 0, change the reset port to 0. Set and Reset cannot both be 0, something unpredictable will happen
- D Latch: safer than SR and notSnotR: no unpredictable state. C port controls whether to take in new internal state value from D.

Highlights:

Transparency: you can see the input from the output, when C is active. This is undesirable for stability
SR Latch with Control pin: additional enabling circuit on the input side
SR Master-Slave Flip-Flop
D Flip-Flop

Highlights:

State Table
- Similar to Truth Table, Input + Present state on the left, Output + Next state on the right
State Diagram
- Models state transition
- State bubbles: one for each state
- Transition: link from one to another state bubble
- Transition condition and output as binary values on next to each transition link

Highlight:

Reset stage: asynchronous and synchronous reset
Design an asynchronous reset D flip flop. I find this easier to use to LogicWork simulation
8 step designing procedure
- Addition to the 5 step for combinational:
  - Step 1: Spec (Same)
  - Step 2: Formulation
    - State Table and State Diagram instead of truth table
    - Can use variables for states in this step
  - Step 3: State Assignment (Next Video)
  - Step 4: Flip-Flop input equation determination (Next Video)
  - Step 5: Output equation determination (Next Video)
  - Step 6: Optimisation (Same)
  - Step 7: Tech mapping (Same)
  - Step 8: Verification (Same)

Highlights:

Step 3: State Assignment
- No unique solution, we only cover two methods
- Sequential Assignment
  - given N states, assign binary values of 0 to N-1 sequentially
  - Require log(n) bits
  - e.g. 6 states, require 3 bits: 000, 001, 010, 011, 100, 101 (or in any other order, all correct but not equivalent)
  - Different order leads to different circuit
- One-hot Assignment
  - given N states, require N bits
  - Each state is N bit, with only a single positive bit, the reset are zeroes.
  - e.g. 6 states, require 6 bits: 000001, 000010, 000100, 001000, 010000, 100000 (or in any other order, all equivalent)
  - Different order leads to identical circuit
Step 4, 5: Flip-Flop input equation determination and Output equation determination
- From state table: Sum-of-Minterm, then optimise
- Use unused states as Don’t Care Conditions
T and JK Flip-Flop
- Can be implemented using D Flip-Flops
- T Flip-Flop
  - Input ports: T, and C
  - Flip internal signal with T is 1
- JK Flip-Flop
  - Input ports: J, K, and C
  - J for Set, K for Reset, just like SR Flip-Flop
  - Flip internal value with J and K are both 1

Highlights:

State Diagrams (Mealy Model) can be inefficient when you have more input/output bits
State Machine Diagrams (Moore Model): Instead of binary values for transitions and output, use Boolean Expressions
- 3 Steps to go from State Diagrams to Moore model
  - Preserve all state bubbles and transition links
  - Translate binary transition conditions into boolean expressions
  - Note the default output values, then add output conditions on Transition Conditions or States